The present invention relates to nonvolatile semiconductor memory devices such as an EEPROM (electrically erasable and programmable ROM) and a manufacturing method therefor.
A full-future-type EEPROM and a flash-type EEPROM are conventionally known as nonvolatile semiconductor memory devices.
FIG. 6 shows a device structure of the full-future-type EEPROM, and FIG. 7 is a circuit diagram showing part of a memory device formed by connecting such devices in a matrix form. As shown in FIG. 6, the full-future-type EEPROM has a memory cell consisting of a memory transistor MTr and a selection transistor STr that are formed in a p-well 2 of an n-type silicon substrate 1. The memory transistor MTr includes a gate structure consisting of a tunnel oxide film 30, a floating gate 31, an insulating film 32 and a control gate 33, and n.sup.+ diffusion layers 34, 35 that are formed in the p-well 2 on both sides of the gate structure. The selection transistor STr includes a gate structure consisting of a gate oxide film 36 and a gate 37, and an n.sup.+ diffusion layers 35, 38.
Referring to FIG. 7, data write, erase and read operations to the full-future-type EEPROM are described below.
The data writing is performed as follows. Positive voltages are applied to a bit line BL and a memory line ML that is connected to the control gate 33 of the memory transistor MTr of the selected device, respectively. At the same time, a positive voltage is applied to a word line WL that is connected to the gate 37 of the selection transistor STr of the selected device, and a source line SL is grounded. As a result, hot electrons generated in the vicinity of the n.sup.+ diffusion layer (drain) 34 of the memory transistor MTr are injected into the floating gate 31 through the tunnel oxide film 30, so that signal charge is written.
The data erasing is performed as follows. A positive voltage is applied to the bit line BL of the selected device, and the memory line ML is grounded. As a result, the charge stored in the floating gate 31 is transferred from the floating gate 31 to the n.sup.+ diffusion layer 34 through the tunnel oxide film 30. Thus, the signal charge is erased.
The data reading is performed as follows. The source line SL of the selected device is grounded, and a positive voltage is applied to the word line WL. At the same time, a positive voltage is applied to the bit line BL of the selected device, and a positive low voltage is applied to the memory line ML. If no current flows through the selection transistor STr in this state, which means that the memory transistor MTr is in a written state, data "1" is read out. On the other hand, if a current flows through the selection transistor STr, which means that the memory transistor MTr is in an unwritten state, data "0" is read out.
Next, a structure of the flash-type EEPROM is described. A stack gate structure of FIG. 8 and a split gate structure of FIG. 9 are two typical structures of the flash-type EEPROM.
The flash-type EEPROM of the stack gate structure as shown in FIG. 8 has a gate structure consisting of a tunnel oxide film 40, a floating gate 41, an insulating film 42 and a control gate 43. N.sup.+ diffusion layers 44, 45 are formed in a p-well on both sides of the gate structure. A p.sup.+ diffusion layer 46 is formed between the n.sup.+ diffusion layer (drain) 44 and the p-well 2 to improve the injection efficiency of hot electrons. Further, an n.sup.- diffusion layer 47 is formed between the n.sup.+ diffusion layer 45 and the p-well 2 to suppress the generation of hot holes due to the interband tunnel effect during the data erase operation.
Data writing to the flash-type EEPROM of the stack gate structure is effected by injecting hot electrons from the vicinity of the drain to the floating gate 41 by applying positive voltages to a gate terminal G and a drain terminal D and grounding a source terminal S. Data erasing is effected by removing signal charge from the floating gate 41 by applying a positive voltage to the source terminal S. (The source terminals S of all the devices on a substrate are connected to each other.) Data reading is effected by applying positive voltages to the gate terminal G and the drain terminal D, and judging whether a current flows between the drain and source.
The flash-type EEPROM of the split gate structure as shown in FIG. 9 has a floating gate 51 on a tunnel oxide film 50 on the side of the drain. A selection gate 53 is formed on the floating gate 51 via an insulating film 52. Data writing to this device is effected by injecting hot electrons into the floating gate 51 by applying positive voltages to a gate terminal G and a drain terminals D. Data erasing is effected by transferring signal charge stored in the floating gate 51 to the drain by grounding or applying a negative voltage to the gate terminal G and applying a positive voltage to the drain terminal D. Data reading is effected by applying a positive low voltage to the gate terminal G and a positive voltage to the drain terminal D, and judging whether a current flows between the drain and source. Since the flash-type EEPROM of the split gate structure has the selection gate 53, there does not occur a problem of excessive erasing as occurs in the flash-type EEPROM of the stack gate structure (described later).
However, the conventional devices having the above structures are associated with the following problems.
In the full-future-type EEPROM, since a single memory cell consists of the memory transistor MTr and the selection transistor STr, the cell area is large, which becomes a disadvantage in realizing a more highly integrated memory device.
While the flash-type EEPROM of the stack gate structure is advantageous in realizing a more highly integrated memory device because of its structure of one transistor per cell, the total erasing time should be set at a longer period based on the erasing period of the device having the longest period required for erasing the signal charge since all cells in a substrate or in a p-well are subjected to the erasing operation at one time. This will cause a phenomenon that the signal charge is excessively removed from devices in which the signal charge erasing completes relatively earlier and positive charge is accumulated in the floating gate 41 of those devices. This phenomenon is called "excessive erasing." The excessive erasing causes a variation in a threshold at the time of the signal charge reading among the devices, which makes the reading operation unstable. For example, when the excessive erasing occurs, a channel is formed even in unselected devices due to the positive charge stored in the floating gate and a current flows between the source and the gate.
On the other hand, in the flash-type EEPROM of the split gate structure, even if the excessive erasing causes the accumulation of positive charge in the floating gate 51, no current flows between the source and the drain because a channel is not formed in the region of the p-well 2 immediately under the selection gate 53. However, because of its device structure, this type of EEPROM is inferior in the integration degree to the flash-type EEPROM of the stack gate structure.
In the conventional EEPROMs shown in FIGS. 6, 8 and 9, the area of the insulating film between the floating gate and the control gate is approximately the same as the area of the tunnel oxide film between the floating gate and the p-well. That is, a capacitance C.sub.D between the floating gate and the control gate is approximately the same as a capacitance C between the floating gate and the p-well. Therefore, a voltage applied to the control gate is equally allocated to the above insulating film and the tunnel oxide film. In order to effectively inject and remove electrons into and from the floating gate, the divided voltage across the tunnel oxide film should be made higher. This can be realized by thinning the insulating film between the floating gate and the control gate to increase the capacitance ratio C.sub.D /C, which, however, will deteriorate the insulation between the floating gate and the control gate to cause a problem of leak current increase.